GENERAL

APPLICATION

PROCESSING



Welcome to the home page of General Application Processing™. Read about the creation of a Flexible System Architecture™ for the next generation of computer, System-On-Chip, and multicore processor design.




NOTE: The new homepage for www.genapro.com is online here.



Screen shot of the FSA™ Simulator thirteen cycles into a CORDIC computation of sine & cosine. Input: 45 degrees. Output: cosine is at top of P1 at level C3, sine is just below it. Both values are .70703125 in a fixed point format with thirteen bits to the right of the binary point.


For fun: click the pic or HERE for an explanation of the CORDIC computing system
Updated — 2008
More serious: click HERE for an architectural "Application Note"




Guest Pages

Brian's CNC Site Brian's Tesla Lab

GenAPro continues to welcome two additions to the site. These areas demonstrate the hard work of Brian Foley and his active mind and hands.





NOTE: The new homepage for www.genapro.com is online here.



Sorry - Trouble with applet, no links here

From the inventor — I created this site in 1999. Except for this home page I have done little to update it since, having plenty of engineering to concentrate on. And yet whenever I reread it I find most parts still hold up pretty well. Even the pages which quote various industry facts and figures from 1998, such as the Executive Summary, illustrate general trends which remain timely.

One item of note about the summary is its size. Although the rule of thumb is to limit an executive summary to at most two pages, I could never get it below five, simply because the scope must cover not merely a single product or widgit, but an entire industry segment.


Multicore — Multicore — Multicore

Ah yes, what would we do without new buzzwords? And yet the fact is, this was a multicore architecture before the term became popular.




Oh No! The end on an era? — A story in the February 15, 2007 EDN talks about how the 16 bit micro world is being assailed from above and below by 32 and 8 bit processors. Is there any hope (or market) left for the sweet sixteens? Actually the article's message isn't quite as drastic as its title, Putting the squeeze on 16-bit processors . implies. While Intel has recently abandoned the 16 bit embedded market, other manufacturers such as Freescale are upgrading their offerings.

The sixteen bit world still offers advantages in power consumption, data-intensive processing, and task-intensive control. Most Digital-Signal Controllers (DSC) are currently 16 bits.

One point for the FSA™ is that it is meant primarily to provide rapid control to logic subsystems on a chip. The data width of such subsystems are not restricted to 16 bits. They can be 32, 64, 1000 bits, any size at all.

And "rapid" is the word for that control: the Flexible System Architecture™ core is a small, nimble sequencer. Most of the instructions decode from memory after only one gate (or mux) delay. And its own control logic is simple. As mentioned below, the FSA™ machine language is its own microcode.




You load sixteen bits, and what do you get — Sixteen bits is the very best word size for low level control; I'm absolutely convinced of this. Yes, if you're doing long computations or need floating point, you'll want more bits, but to control something? If you need more than 16 bits, you aren't thinking the problem through! Compared to 32 bits, a 16 bit core takes up less die space (especially when busing is factored in), runs cooler (and therefore slightly faster), has half the leakage current, and is easier to program, allowing for faster design cycles.

"The 16-bit-microcontroller market lackes a standard architecture that dominates the device space; it comprises proprietary architectures." — EDN Magazine, February 17, 2005 (see: Reaching down: 32-bit processors aim for 8 bits ). While 8051 clones dominate at eight bits and the ARM architecture rules the 32-bit embedded world, nobody seems able to grab more than 20% of the $4-billion and growing (2004) sixteen bit market. It's the Wild West: a frontier of opportunity.




Almost ready for Prime Time — I have completed Version 7 of the FSA™ Simulator, an admittedly bare-bones yet workable C-language based software development system. I'm working on updating documentation and IP protection, and then ... ?



An Open Letter

Dear Visitor –

This IS the future of computing: A parallel architecture with an enforced hierarchy for true security, implemented as plug-in modules simular to memory units today. It may or may not turn out to be the Flexible System Architecture™ that leads this revolution, but the days of the current commercial offerings have to be numbered.

This is a very flexible computing approach. In some ways, it's similar to ASIC technology, but more structured. One could say ASIC is working with a blank sheet of paper, while this invention is working with graph paper. On the other hand, this new approach provides much more design freedom than trying to work within the block diagrams of conventional processors. If I were to sum it up in two words, I would call it a "control architecture."

Probably the most unique property of the FSA™ is that its microcode and assembly languages are one and the same; yet, while drawing on the power of microcode, it remains an easy to learn, small word environment. Internally, this results in a fragmentation into a very fine-grained parallel processing system, mathematically scaleable from this detailed world of low level circuitry up to (theoretically) any size computer.

Enough about technology. What are its market possibilities? Being a general-purpose item makes its payoff potentially huge. The same modular design can do work ranging from simple appliance control to supercomputing. The main downside is that the development cost for universal computer architectures also runs very high. Somewhat alleviating this is that it doesn't have to address every possible application area at once; it can stand in and hit singles awhile before it swings for a grand slam.

There is another aspect to the FSA™ having to do with its unique layout when multiple processors are used for parallel processing. I believe that highly secure systems can be developed around such an array. I am not an expert in such systems so I may be going out on a limb here, but the instruction set lends itself to a very tightly controlled hierarchical layering, with lots of checks and monitoring possible.

I'm the classic lone inventor operating with minimal resources and few industry contacts, but with a competitive product only a short development stretch away from market. My ultimate aim is to implement the full FSA™ design (it's not all that large). Some early versions may be smaller to save costs (and size & power), but I wish to be associated with people who become passionate about ultimately creating the complete system.

– Bob Loy, Founder




Feel free to wander through the links at random, or take one of two GUIDED TOURS, through either the business side of things or the technical side. Just click on one side or the other...

Marketing Tour / Technical Tour



Java cooled off? Jump to the text-only Site Map